1. Field of the Invention
The present invention relates to an emulation system, and more specifically to a microcomputer emulation system which makes it easy to construct an emulation chip set.
2. Description of Related Art
At present, demands for microcomputer-applied electronic instruments including home electronic instruments and office automation instruments are increasing. These electronic instruments are rapidly becoming high performance and high function, and also remarkable in versatility. As a result, it has become necessary that microcomputers have a specification specialized to each of makers of the electronic instruments and further specialized to each of the electronic instruments themselves.
On the other hand, competition among makers becomes fierce. Therefore, in order to shorten a turn-around time (TAT) in product development, a development tool including a microcomputer emulation system for assisting development and debugging of user's programs has become important in the process of developing a microcomputer-applied system.
At present, microcomputers specialized to application fields and/or application systems are mainly comprised of an ASIC (application specific integrated circuit) microcomputer in which a high performance CPU is integrated as a core element on a single chip together with various peripheral function units suitable or specialized to a maker or user.
In the prior art, therefore, the above mentioned microcomputer emulation system has been developed, for each developed microcomputer, together with a special evaluation chip which is to be provided in the emulation system and which performs the same operation as that of the developed microcomputer. Accordingly, it has been necessary to provide a similar evaluation chip for the ASIC type microcomputer.
For efficiently realizing the above mentioned demand, there has been known one method of preparing a CPU evaluation chip comprising a CPU core unit used in common to various products and a peripheral evaluation chip comprising a peripheral function unit which is different in each of products, and then providing a the chip-set structure comprised the CPU evaluation chip and the peripheral evaluation chip.
Referring to FIG. 1, there is shown one example of the above mentioned chip-set structure of the emulation system. The shown emulation system is generally designated with Reference Numeral 100, and comprises a CPU evaluation chip 101 including therein a CPU 104A. This CPU 104A performs the same operation as that of an internal CPU included in an actual developed microcomputer product, which will be called a "product chip."
The CPU evaluation chip 101 is connected through a peripheral bus 102 to a peripheral evaluation chip 103. Operation timings of the peripheral bus 102 to the peripheral evaluation chip 103 are entirely the same as those of an internal bus coupling between an internal CPU and a peripheral unit in the product chip.
The evaluation chip 103 in the example shown in FIG. 1 comprises the product chip itself. Namely, the product chip itself includes an internal CPU 104B and a peripheral function unit 105 included in the peripheral evaluation chip 103. The product chip has two kinds of operation mode, namely, an operation mode of the product chip itself and an evaluation operation mode.
In the product chip operation mode, the CPU 104B is coupled through an internal bus 106 to the peripheral unit 105 as shown by the ghost line in FIG. 1, so that a normal operation is performed. In the evaluation operation mode, on the other hand, the CPU 104B is electrically isolated from the internal bus 106, and a portion of the internal bus 106 is coupled to the peripheral bus 102.
The product chip operation mode and the evaluation operation mode of the product chip are alternatively designated through a mode designation terminal 107. For example, if the mode designation terminal 107 is set to a logic value "0" connected to ground, the product chip operation mode is designated. If the mode designation terminal 107 is set to a logic value "1" connected to a voltage supply voltage, the evaluation operation mode is designated. The evaluation chip 103 shown in FIG. 1 is in the evaluation operation mode.
In the evaluation operation mode, various controls (including a data read/write control) to the peripheral function unit are emulated in the emulation system by accessing through the peripheral bus 102 and the internal bus 106 to the peripheral function unit 105 internally provided in the peripheral evaluation chip 103, under instruction execution of the CPU 104A in the CPU evaluation chip 101.
Here, connection and access to an external memory and an I/O device, which are not shown, are performed through a system bus 108 provided to the CPU evaluation chip 101. Terminal function corresponding to the peripheral function unit 105 is realized by a peripheral function signal 109 of the peripheral evaluation chip 103.
The system bus 108 and the peripheral function signal 109 are connected to an external device through a system bus terminal 110 and a peripheral function terminal 111 of the emulation system 100.
The peripheral evaluation chip 103 is made to cause only the peripheral function unit 105 to effectively operate for the product chip. Function of the product chip corresponding to terminals switched to the peripheral bus 102 is substituted with functions provided in the CPU evaluation chip 101.
In the chip-set structure of emulation system 100, it is sufficient if only a product chip is developed for each application. Namely, it is unnecessary to develop a specialized evaluation chip for each application. Accordingly, it is advantageous in that an effective development environment is given to users.
Lastly, however, rapid advance of semiconductor manufacturing techniques is making it possible to utilize a 0.5 .mu.m process, and therefore, it is becoming possible that a user specific logic circuit on the scale of several thousand to several ten thousand gates, which had been manufactured on a separate substrate, are integrated together with a microcomputer on a single ship.
One example of this type microcomputer is proposed in Japanese Patent Application Laid-open Publication No. JP-A-03-058141, which discloses an integrated circuit with a user's logic. This integrated circuit can be independently connected to respective external terminals, when an additional user's logic circuit is connected to the existing microcomputer.
Here, the user specific logic circuit has an extremely high level of versatility in comparison with the peripheral function units of the conventional ASIC microcomputers, so that it can be different not only from one user to another, but also from one instrument to another. However, how to construct an emulation system for emulating this integrated circuit with the user's logic has become a problem.
In order to overcome this problem, there has been proposed to prepare a gate array of PLD (programmable logic device) which operates equivalently with a user specific logic circuit, and to combine the gate array or PLD with a conventional emulation system.
Referring to FIG. 2, there is shown a block diagram of an emulation system 200 constructed by adding a gate array 201 for a user specific logic circuit, to the emulation system 100 shown in FIG. 1. In the emulation system 200 shown in FIG. 2, therefore, the gate array 201 is newly developed independently of the product chip, and is required to be developed for each user and for each instrument, so as to correspond to a user specific logic circuit included in the product chip.
The gate array 201 is connected to the CPU evaluation chip 101 through the system bus 108, so that various controls (including the data read/write control) to internal hardware are performed by instruction execution of the CPU.
An internal circuit of the gate array 201 is constructed to be able to perform an operation equivalent to that of the user logic internally contained in the product chip. In addition, a user logic terminal 203 is provided for inputting and outputting a user logic signal to and from the gate array 201, so that the functions corresponding to the user logic circuit included in the product chip are emulated.
As mentioned above, for emulation of the microcomputer having the CPU and the user specific logic circuit integrated together on a single chip, the conventional emulation system has required to newly prepare a gate array corresponding to the user specific logic circuit.
Therefore, at each time a microcomputer is newly developed, it was necessary to develop a special gate array corresponding to the user specific logic circuit newly added to the developed microcomputer. Accordingly, the development steps and cost for design, manufacturing and evaluation of the special gate array have been required. This problem is an important problem to be solved for microcomputer developers and manufacturers and also for users of microcomputers or microcomputer development orderers.
In general, it is very difficult to make a circuit realized on a gate array completely consistent with another circuit formed on a single chip microcomputer, in physical locations and wiring patterns of transistors, although these circuits have the same logical circuit construction. In addition, it is substantially impossible to cause these circuits to operate in the same electrical conditions including input/output of signals terminals. As a result, the conventional emulation system cannot give a completely satisfactory emulation environment.